Intel senior fellow Mark Bohr showed off the company’s revolutionary new 3D transistors in an announcement this week in San Francisco. The power, performance, and real estate gains are impressive. Moore’s Law seems to be holding.
In the video below, Bohr explains that these transistors are normally built in a two-dimensional fashion, where electrons flow from one end of a transistor to another in a planar way. With the Tri-Gate transistors, they flow sideways, then up, then across and then down again. This allows the transistor to take up less space on a chip, the same way a skyscraper is a more efficient use of a plot of land.
The video is well done, fun, and worth watching.
From the press release:
Intel today announced a significant breakthrough in the evolution of the transistor, the microscopic building block of modern electronics. For the first time since the invention of silicon transistors over 50 years ago, transistors using a three-dimensional structure will be put into high-volume manufacturing. Intel will introduce a revolutionary 3-D transistor design called Tri-Gate, first disclosed by Intel in 2002, into high-volume manufacturing at the 22-nanometer (nm) node in an Intel chip codenamed Ivy Bridge. A nanometer is one-billionth of a meter. The 22nm 3-D Tri-Gate transistors provide up to 37 percent performance increase at low voltage versus Intel’s 32nm planar transistors. This incredible gain means that they are ideal for use in small handheld devices, which operate using less energy to “switch” back and forth. Alternatively, the new transistors consume less than half the power when at the same performance as 2-D planar transistors on 32nm chips.
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Great fun!
The “real” 3D breakthrough will come when circuits can be layered within a chip, with vertical connections as well as horizontal. Dumping heat from them is a problem, however!
Thanks, Anthony. Wonderful!
Haven’t folks made 3-D transistors before? Things with a V shape?
Oh, wait, they have:
http://www.patents.com/us-6078078.html
so this is more of a “we made it square instead of a V” announcement…
Um, I guess this is a marketing announcement?
People have a hard time in the practical world with understanding electricity and physics. I remember reading with amusement old PCWorld articles where they were afraid of “quantum forces” or “quantum physics” coming into play if you tried to make transistors in a pathway much narrower than whatever we had when their current article was written (65nm, then 45nm, etc.) They seemed amazed that there has been no REAL problem, other than in manufacture capability, for very small transistors and that laws of physics work in such a small setting. If we can just stack it, squish it, or cool it, then things can get very small indeed – and still work!
This is awesome. Intel’s research labs deserve major kudos for bringing us a little closer to the Singularity. However, this advance in transistor technology, as impressive as it it, is not nearly enough to solve the biggest crisis in the history of the integrated circuit: the memory bandwidth crisis. The cores in a modern multicore processor access the common main memory via a single mechanism or controller. This means that only one core can have read/write access at a time. This is known as the memory access bottleneck. The result is that memory bus contention causes a degradation in performance that increases nonlinearly with the number of cores on a chip. It quickly gets to the point where it completely destroys the performance benefits of having multiple cores.
As you know, nobody messes with Moore’s Law and survives to brag about it. Unless someone comes up with a way for multiple cores to have simultaneous access to memory without contention, it’s goodbye Moore’s Law, hello dwindling profits! Intel had better be spending a lot money to come up with a solution because whoever is the first to do so will ride the next computer revolution wave for at least a decade.
In my opinion, the computer industry is on the threshold of a radical revolution that will discard most of the old ideas about how computers should be designed and programmed, ideas that are precious to the boomer geek generation. Soon it will be time for the Turing Computing Model to join the slide rule and the horse whip at the Smithsonian.
The V-Gate transistor in your link was patented by AMD, a competitor of Intel, the maker of the new Tri-Gate transistor in this announcement.
I wonder if some corporate
spyingsnooping was going on.Probably, it seems that Intel want a piece of the action in the Tablet and cell-phone market.
One thing I love about electronics is that they are still evolving at a pace that few other fields can dream of.
Game Changer
Any idea when these things will be running in Trinary?
E.M.Smith says:
Haven’t folks made 3-D transistors before? Things with a V shape?
Oh, wait, they have:
http://www.patents.com/us-6078078.html
so this is more of a “we made it square instead of a V” announcement…
Um, I guess this is a marketing announcement?
No, this is a “put into high-volume manufacturing” announcement. As the article pointed out, Intel first announced their Tri-Gate concept in 2002. Now, they’re rolling it out into commercial production.
EMSmith – That was a patent which doesn’t necessarily mean that the V-gate transistor was actually made. Intel are now saying that they have made it, though rectangular rather than V. It could be that they made it rectangular rather than V to avoid patent issues.
At the dimensions they are producing these transistors a V-shape or rectangular shape is just semantics. I’m guessing neither descriptions are strictly correct in describing the actual shape of the gate electrode.
As I understand it, the lithography process is still 2-D whereby a process of layering achieves the triple gate, hence 3-D. I’d like to know how one would achieve a gradient necessary for a V-channel. Anyone: is this being done already?
more efficient in space, less efficient in cooling and production.
more efficient in destroying such stupid old fashioned things as life outside of the box.
The switching characteristics of a field-effect transistor are based on the interaction of electrostatic forces from the gate controlling the (electrically isolated) electron channel. A V-gate transistor would have very different characteristics between the top of the V and the wide bottom, producing an averaged and less than maximum improvement and probably difficult process control. The U-channel design, with its flat sides, provides uniform response from top to bottom, which is the key. And yes, they can build devices that small with precise shapes, accurately repeated billions of times on every chip.
My guess is that AMD didn’t build V-channel devices because they just didn’t work that well and/or were difficult to make.
As for the Turing Model, there is much room for the improvement of programming languages, but Turing simply proved that any mathematical problem could be solved by mechanical/electrical “computers” and showed a method for doing so. If anyone out there has an alternative, please don’t keep us and history in suspense – show your method!
The macro parts of the film were nice (Honey, I shrunk the Bohr) , but their animation of the transistor itself wasn’t very good. The flow didn’t change when the gate was charged.
22 nanometers is more impressive than 3D. Not that many years ago, 3 micron geometry was state of the art. And 64K DRAMS were pie in the sky. There will be a limit, I rather doubt transistors can get smaller than one atom, probably take at least three or four, so 5 nm may be a hard limit. Lithography also limits, but 22 nm is far less than 1 wavelength of anything close to light. And it seems to work.
I agree on the memory bandwidth comment. Even my old duo-core processor runs into that. Large internal caches may help. A bigger question: how much processing power do we really need, and how much is ‘fluff’? (doing things for the sake of doing them) Still impressive, Moore’s law has held up (more or less) for over 40 years.
Now if batteries could do that, we’d have some really neat stuff…
3D transistors are old news, very old news. In 1961 Motorola invented the Mesa transistor – with etching to separate the base, emitter and collector on little mesas. It was the first transistor with an f-tau of over 100 megaherz (megacycles in those days).
“Honey, I shrunk the engineer!”
At that size his ability to do QA on selected components should be greatly increased.
Good stuff, the capability of creating Skynet moves that much closer.
/end_goofiness
It is very interesting times again.
On the one hand we’re back to square one at chasing the ram multiplier, 4, 8, 16, 32 GB instead of MB.
On the other hand a new chase is on where we instead of chasing frequency are chasing cores, and soon there’ll be affordable 8, 12, 16, …, cores, pretty much what happened with GPU’s. But now we’re talking about real computing power, the amount of different calculations per cycle at gigahertz speed and even for pesky laptop computers no less, for a $1000. And to think just 16 years ago we spent a small fortune on craptop95’s and small countries whole treasure department on a few single core, megahertz retarded, 64-bit sparc ultras and Alpha stations (and that’s probably the definition of insanity.)
:p
Brian H says:
May 6, 2011 at 9:28 pm
The “real” 3D breakthrough will come when circuits can be layered within a chip, with vertical connections as well as horizontal. Dumping heat from them is a problem, however!
—
Well they already are, or are you talking about having multiple planes of silicon? That’s possible too if you want to dope poly, but you won’t get very good transistors out of it. Or, you could do 3D by bonding multiple chips together with vias which is being done on small scales now. You still have planar processing so aside from not having to go outside the chip package I’m not really sure what the gain is.
“With the Tri-Gate transistors, they flow sideways, then up, then across and then down again. This allows the transistor to take up less space on a chip, the same way a skyscraper is a more efficient use of a plot of land.”
—
No. The gate becomes a 3D structure but the channel is essentially the same. Current still flows directly from the Source/Drain to the Drain/Source. They show it with a different aspect ratio, but it’s really no different than turning the channel on its side. The key, as they correctly described in the video, is that the gate now wraps around 3 sides of the channel allowing much better control. In a perfect world you would wrap it completely around the channel. A weak analogy is to think of trying to hold a spoon in your hand. You’ve got much better control wrapping your fingers around it than simply resting the spoon on top of your hand and trying to scoop something up.
It is a mass production achievement, but the concept has been discussed for a long time.
I remember when the 1K memory chips came out. I said that it was a massive amount of memory and I couldn’t see them getting any larger than that.
Later the 1M memory chips came out; again I felt that the memory was so large, it couldn’t get any larger than that!!!
Today, I just keep my mouth shut and wonder in amazement….